Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5733002
Kind Code:
B2
Abstract:
An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.
Inventors:
Naoki Itani
Application Number:
JP2011100820A
Publication Date:
June 10, 2015
Filing Date:
April 28, 2011
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H01L21/3205; H01L21/768; H01L23/12; H01L23/522
Domestic Patent References:
| JP11195706A | ||||
| JP2010080781A | ||||
| JP2009021604A | ||||
| JP2004335647A |
Foreign References:
| US20100308471 | ||||
| US20090014888 | ||||
| US20020163072 |
Attorney, Agent or Firm:
Mitsuharu Kawakami