MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR DESIGN APPARATUS

Japanese Patent JP2006186150

A

To provide the manufacturing method of a semiconductor storage device and a semiconductor design apparatus capable of realizing ease of design or reduction in a design period.

In the case of verifying a designed memory array for example, the manufacturing method uses a read signal quantity VS_EFF of a memory cell formalized by functions of various parameters VN(ΔVBDL), VN(ΔVTN), VN(IJ) including various distributions, calculates the value of the read signal quantity VS_EFF by using values extracted at random from the distribution of each of the various parameters, discriminates the propriety of the memory cell on the basis of a result of the calculation, and applies the calculation of the value of the read signal quantity VS_EFF and the discrimination of the propriety of the memory cell to many memory cells provided with the memory array. Consequently, a total number of defective bits or the like obtained by the above process is used for an evaluation criterion of the memory array.

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AKIYAMA SATORU
SEKIGUCHI TOMONORI
KAWAHARA TAKAYUKI
KAJITANI KAZUHIKO

JP2004379071A

July 13, 2006

December 28, 2004

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HITACHI LTD
ELPIDA MEMORY INC

H01L21/82; G06F17/50; H01L21/00; H01L21/8242; H01L21/8244; H01L21/8247; H01L27/105; H01L27/108; H01L27/11; H01L27/115

Yamato Tsutsui

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