Title:
MANUFACTURING SEMICONDUCTOR
Document Type and Number:
Japanese Patent JPS5575219
Kind Code:
A
Abstract:
PURPOSE:To form source-drain regions and a channel by one high-temperature thermal treatment, by forming the first-solid layer containing impurities of a specified density on a semiconductor substrate and selectively removing the layer, thereafter forming the second-solid layer containing impurities whose density is different from the first-solid layer. CONSTITUTION:An SiO2 film is deposited on a p-type Si substrate, and source- drain diffusing windows 2a and 2b are provided. A poly-crystal-Si-gate-electrode wiring 4 is formed on a remained SiO2 film 3. Then, a PSG layer 5 is deposited all over the surface by a gaseous-phase growth method. Etching is performed by a mixed gas of CF4 and O2 with a resist pattern as a mask, and portions 6 which are adjacent to the windows 2a and 2b are removed. Thereafter, a PSG layer 7 whose density is lower than that of the layer 5 is grown again all over the surface including the windows. The thermal treatment is made in an N2 gas of 1,000 deg.C, and impurities in the layer 7 is diffused, thereby n-source-drain regions 8 and 9 are formed. At the same time, impurities are also diffused from the layers 5 and 7, and a channel is formed below the wiring 4.
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Inventors:
MIMURA SHIYOUICHI
Application Number:
JP14945278A
Publication Date:
June 06, 1980
Filing Date:
December 02, 1978
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L29/78; H01L21/225; H01L21/3205; H01L23/52; (IPC1-7): H01L21/225; H01L21/88; H01L29/78