Title:
【発明の名称】マトリクス網回路
Document Type and Number:
Japanese Patent JP3112208
Kind Code:
B2
Abstract:
PURPOSE:To reduce the entire contention arbitration time and a transfer path for various data by forming a large scale matrix switch with sets of lots of small scale matrix switches and processing contention arbitration in parallel through divided processing. CONSTITUTION:Groups of divided request generating sources R1-R8 and resources S1-S8 are mutually connected by each of small scale matrix switches G(1, 1)-G(4, 4) respectively. Through the constitution above, access requests and/or data from the request generating sources R1-R8 are directly transferred to the matrix switches G(1, 1)-G(4, 4) interconnected by input side connection lines L1-L8, and the access requests and/or data from the matrix switches G(1, 1)-G(4, 4) to the resources S1-S8 are directly transferred to the resources S1-S8 interconnected by output side connection lines LO1-LO8. Thus, number of passing cross points is decreased and the contention arbitration is implemented in parallel by using each small scale matrix switch, then the entire processing speed is quickened.
Inventors:
Kenichi Endo
Naoaki Yamanaka
Yukihiro Doi
Koichi Genda
Naoaki Yamanaka
Yukihiro Doi
Koichi Genda
Application Number:
JP26503292A
Publication Date:
November 27, 2000
Filing Date:
October 02, 1992
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H04Q3/52; G06F13/36; G06F13/362; H04L12/28; (IPC1-7): H04Q3/52; G06F13/362; H04L12/28
Attorney, Agent or Firm:
Naotaka Ide (1 person outside)