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Title:
MARKING AND ALIGNMENT MARK THEREOF
Document Type and Number:
Japanese Patent JPS6229138
Kind Code:
A
Abstract:

PURPOSE: To scatter and minimize any alignment errors between processes by a method wherein two kinds of alignment marks are made by making alignment mark making processes multiple while each alignment mark is aligned by scanning in the process making respective alignment marks.

CONSTITUTION: Alignment marks 41 and 42 are formed and then scanned along scanning lines 43 to detect the edges thereof. When the alignment marks 41 and 42 are made respectively in active process and gate process while both active region and gate region require the alignment in contact process, contact pattern aligns both patterns to minimize respective errors. The scanning lines are represented by arrow marks while an alignment mark 44 of mark is formed into a square window 44a in the central part thereof. The marking process is performed to meet the requirements of x1=x2 and 1=y2. Finally the alignment marks 41 in the active process are made in a field oxide layer while the alignment marks 42 in the gate process are made in a polysilicon layer to be a gate electrode.


Inventors:
ITO YOSHIO
OTSUKA HIROSHI
TAGUCHI TAKASHI
Application Number:
JP16743785A
Publication Date:
February 07, 1987
Filing Date:
July 31, 1985
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L21/30; G03F9/00; H01L21/027; H01L21/67; H01L21/68; (IPC1-7): G03F9/00; H01L21/30; H01L21/68
Attorney, Agent or Firm:
Hiroshi Kikuchi