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Title:
MASTER SLICE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP01175241
Kind Code:
A
Abstract:

PURPOSE: To shorten the turnaround time by shortening a manufacturing process as compared with a conventional process by a method wherein a contact pattern and up to a first-layer wiring pattern are formed as fixed patterns and only a via hole pattern and a second-layer wiring pattern are changed so that various circuits having prescribed functions can be formed.

CONSTITUTION: A contact hole and a mask pattern of a first wiring film are formed as fixed. At least one each of a contact hole 20 is made in respective individual regions in such a way that it can be connected electrically to individual regions of a transistor, i.e. P-type and N-type sources and drains 12W14, 15W17 and gates 10, 11. A partially expanded part 19 is formed on a first wiring part 18 in such a way that a via hole can be received properly; at least one each of this expanded part is formed on individual regions (source, drain and gate). The first wiring film is formed via said contact hole in such a way that it is properly connected electrically to said regions (source, drain and gate).


Inventors:
Sato, Shinji
Application Number:
JP1987000332240
Publication Date:
July 11, 1989
Filing Date:
December 29, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/3205; H01L21/82; H01L23/52; H01L27/118; (IPC1-7): H01L21/82; H01L21/88



 
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