Title:
MASTER SLICE SUBSTRATE
Document Type and Number:
Japanese Patent JPS57117254
Kind Code:
A
Abstract:
PURPOSE:To reduce the area of wiring region, chip size and the number of through-holes, by making the positions of terminals of two adjacent cells interposed with each other. CONSTITUTION:A unit cell 2 consists of a element region 4 and a wiring region 3, and terminal 6a1-6a5 and 6a'1-6a'5 in the cell are provided also in the wiring region 3, not only in the element region 4. The terminal 6a'1-6a'5 of a unit cell 2a and the terminals 6b'1-6b'5 of a unit cell 2b are provided in a common wiring region 3, interposing each other. The connection wiring 10 and 11 for the unit cells 2a and 2b, the connecting wiring 9 for unit 2a and 2c, the connection wiring 12 for a unit 2b and 2d are performed only in the wiring layer of the direction X.
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Inventors:
KAKIMOTO MASAO
Application Number:
JP430881A
Publication Date:
July 21, 1982
Filing Date:
January 14, 1981
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/822; H01L21/82; H01L27/04; H01L27/118; (IPC1-7): H01L27/04
Domestic Patent References:
| JPS5432085A | 1979-03-09 | |||
| JPS56118350A | 1981-09-17 |