MATCHED FILTER DEVICE

Japanese Patent JP2944492

B2

PROBLEM TO BE SOLVED: To attain low power consumption and high speed processing by using multipliers of two series obtained by every other PN codes for multipliers for n-sets of matched filter circuits and sampling input signals to each of n-sets of the circuits cyclicly for each one-tip time and obtaining an output sum of all the matched filters.
SOLUTION: Matched filter circuits MF1, MF2,..., MF4 of two sets of two each are provided and the circuits have the number of taps being a half of the PN codes, set a PN code be PN(i), then the matched filter circuit is provided corresponding to odd and even series of the PN code input signal and PN(i) is set to the MF1, MF2 as a multiplier. Then a clock CLK1 of a frequency being a half of the chip rate is fed to the MF1, MF2 and a clock CLK2 being the inverse of the CLK1 and with a same frequency is given to the MF2, MF3. Let outputs of the circuits MF1 to MF4 be Vo1 to Vo4, then the Vo1, 2 are given to an adder circuit AUM 11 and the Vo3, 4 are given to an adder circuit SUM 12 and they are alternatively outputted.

SHU NAGAAKI
KOTOBUKI KOKURYO
YAMAMOTO MAKOTO
URABE KENZO
TAKATORI SUNAO

JP31577195A

September 06, 1999

November 10, 1995

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KOKUSAI DENKI KK
TAKATORI IKUEIKAI KK

H03H15/00; H03H11/04; H03H17/02; H04B1/7093; H04J13/00; (IPC1-7): H04J13/00; H03H15/00

JP61153764A
JP62159271A
JP212456A
JP758669A
JP946174A
JP946231A
JP983483A
JP983486A
JP983488A
JP9116522A
JP9116523A
JP9130365A

Yamamoto Makoto

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