Title:
MAXIMUM LIKELIHOOD SERIES ESTIMATING DEVICE
Document Type and Number:
Japanese Patent JP3244722
Kind Code:
B2
Abstract:
PURPOSE: To omit troublesome processing in a conventional device that a point of agreement is obtained with respect to a bit error rate through simulation and a sampling phase is identified.
CONSTITUTION: A likelihood or a square sum of a training series (&phiv n) corresponding to a training series (&phiv n) of a sample value series of a reception signal y(t) is calculated when sampling is implemented at a phase of plural different sampling phases, a sampling phase τmax in which the likelihood or the square sum is maximized is selected by a sampling phase selection section 110 and the result of selection is fed to a sampling processing section 120. The processing section 120 applies sampling to the reception signal y(t) at the sampling phase τmax and the sample series (yn) is fed to a Viterbi algorithm processing section 130 and a transmission line estimate section 140. The Viterbi algorithm processing section 130 and the transmission line estimate section 140 estimate a transmission symbol series (EXn).
Inventors:
Genhiro Shiino
Yamaguchi Norio
Masami Abe
Yamaguchi Norio
Masami Abe
Application Number:
JP18642691A
Publication Date:
January 07, 2002
Filing Date:
July 25, 1991
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H04L25/08; H03H15/00; H03H17/00; H03H21/00; H03M13/23; H03M13/41; H04B3/04; (IPC1-7): H03M13/41; H03H17/00; H04L25/08
Domestic Patent References:
| JP6321243A | ||||
| JP210924A | ||||
| JP58215154A | ||||
| JP2192252A | ||||
| JP4321338A | ||||
| JP5316083A |
Attorney, Agent or Firm:
Yasunari Kakimoto