Title:
MECHANICAL LOAD TEST METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3618559
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable a test including a three-dimensional deformation effect in a fatigue test of a soldered part by developing bending in the plural directions by a mechanical load on a semiconductor device used as a test piece.
SOLUTION: A semiconductor device 3 used as a test piece has an electronic device composed by surface mounting of a semiconductor package 1 having a structure jointed with a chip 4 through solder bumps 6, on the center part on a square circuit board 2 (or a mother board). The semiconductor device 3 is four-point supported on a support stand 8 by support parts 9, and a concentrated load is loaded on the center part thereof by a load application mechanism part 10. Hereby, three-dimensional deformation is developed on the semiconductor device 3 and it becomes more similar to a deformation mode in a thermal load. A relation chart between the load detected by a load cell 11 and a changed quantity detected by a displacement meter 13 is acquired. In this case, if the repeated deformation is given, an electric resistance is measured simultaneously by a junction electric resistance measuring apparatus 15, to thereby confirm electric conductivity at the junction.
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Inventors:
Kenji Hirohata
Kawamura Hoyasu
Kawamura Hoyasu
Application Number:
JP27160398A
Publication Date:
February 09, 2005
Filing Date:
September 25, 1998
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G01R31/02; G01M99/00; G01N3/34; (IPC1-7): G01N3/34; G01M19/00; G01R31/02
Domestic Patent References:
| JP9243702A | ||||
| JP8111360A | ||||
| JP727810A | ||||
| JP4175671A | ||||
| JP10213531A | ||||
| JP60173053U | ||||
| JP555356U | ||||
| JP52116981U | ||||
| JP3109148U |
Attorney, Agent or Firm:
Takehana Kikuo
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