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Title:
MECHANISM TO EXTEND COMPUTER MEMORY PROTECTION SCHEME
Document Type and Number:
Japanese Patent JP2008282417
Kind Code:
A
Abstract:

To provide an apparatus and a method that enable a central processing unit (CPU) to extend the protection schemes afforded to virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable of providing while at the same time preserving compatibility with legacy operating system software.

The apparatus includes a translation lookaside buffer (TLB) and extended protection logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries, each of which has a flags field and an extended flags field. The extended protection logic is coupled to the TLB. The extended protection logic specifies legacy access restrictions according to the flags field, and specifies the extended access restrictions according to the flags field in combination with the extended flags field. Specification of the legacy access restrictions preserves compatibility with a legacy virtual page access protection protocol.


Inventors:
ANDERSSON PETER KOCH
KISSELL KEVIN D
Application Number:
JP2008176897A
Publication Date:
November 20, 2008
Filing Date:
July 07, 2008
Export Citation:
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Assignee:
MIPS TECH INC
International Classes:
G06F12/10; G06F12/14; G06F21/62; G06F21/79
Domestic Patent References:
JP2001056783A2001-02-27
JPH06139147A1994-05-20
JPS60221851A1985-11-06
JPH02238534A1990-09-20
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo