To reduce a circuit size by reducing performance deterioration of a CPU to shorten an access cycle to a memory, if two or more access sources to the memory exist, in a memory access control circuit capable of performing access control to the memory.
Between an image compression device 3 and the memory access control circuit 5, a bus 8 dedicated to images is provided independently of a CPU bus 7, and the image compression device 3 can get access to the memory 4 independently of access from the CPU 1 to the memory 4. In addition, by continuous access determination and by including a bus sizing function, the shortening of the access cycle is realized, and the circuit size can be reduced by using signal input from the outside to generate refresh timing to the memory 4.
Tomoyasu Sakaguchi
Hiroki Naito
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