PURPOSE: To allow a CPU to make access to a fast DRAM without executing a waiting cycle by controlling a DRAM access by an access clock obtained by multiplying a reference clock generated from the CPU.

CONSTITUTION: When a reference cock is inputted from the CPU to a clock multiplying circuit 1, the circuit 1 supplies a multiplied memory access control clock to an input latch circuit part 38, a refresh timer circuit part 39, an arbiter circuit part 41, and a timing generator circuit part 42 to operate the clock as a reference clock for memory access. Consequently, a timing signal for DRAM access can be fractionally and accurately generated, an ordinary waiting cycle can be removed at the time of generating a memory access request from the CPU and memory access matched with the speed of the CPU can be efficiently executed.