PURPOSE: To provide a memory access controller for operating only the arbitrary bit of a memory by providing a bit selecting means for accessing the desired bit of data stored in the memory based on address information generated from a CPU.

CONSTITUTION: The CPU is connected through an address bus 2 to an access control circuit 5. The input terminals of AND gates a0-a7 are connected to the output terminals of an address decoder 6 of the control circuit 5, in the case of an address to access respective bit memories m0-m7 while receiving high-order bits A8-An of address information, a high-level signal is inputted and in the case of any other address, a low-level signal is outputted. Low-order bits A0-A7 of the address information are connected to the respective other input terminals of the respective AND gates a0-a7. Thus, the desired bit of data stored in the respective bit memories m0-m7 can be accessed based on the low-order bits A0-A7 of the address information.