Title:
MEMORY ACCESS DEVICE
Document Type and Number:
Japanese Patent JPS61188656
Kind Code:
A
Abstract:
PURPOSE:To access even under differing memory capacity conditions by variably setting decode conditions by a firmware and also variably setting the address for accessing from an existing processing system processor to an additional system memory. CONSTITUTION:When a microprocessor (MPU) 1 accesses a memory 7, the program of an MPU 1 sets the leading address of the memory 7, for example, the predetermined upper bits 2 of an address 2,000 in a leading address register 8. When the address 2,000 transmitted to a bus 4 and the address 8 of the register 8 coincide with each other as the program proceeds, a coincidence circuit 9 issues a coincidence signal so that the right of using the bus 12 is transferred to the existing processing system processor 1. The firmware is set so that the driver/receiver 10 converts by this coincidence signal the address 2,000 to an address 1,000 of the memory 7 by MPU 6. A data driver/receiver 11 is also enabled. Hence, the memory 7 of the MPU 1 can be accessed while data read and write operations can also be executed.
Inventors:
TANAKA MINORU
Application Number:
JP2780285A
Publication Date:
August 22, 1986
Filing Date:
February 15, 1985
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F12/00; G06F12/06; G06F13/16; G06F15/16; G06F15/177; (IPC1-7): G06F12/00; G06F15/16
Attorney, Agent or Firm:
Furuya Fumio