Title:
MEMORY ACCESS SYSTEM BY MULTI-DDA
Document Type and Number:
Japanese Patent JPS62182882
Kind Code:
A
Abstract:
PURPOSE:To display picture at a high speed by dividing the segment display with plural digital differential analyzers and writing these divided segment displays in parallel and with allotment. CONSTITUTION:A segment dividing circuit 3 calculates the tilt value of a segment to be displayed and divides the number of dots forming the segment to be displayed by (n) to attain the equal division with a single difference if said dot number is not divisible. Furthermore the circuit 3 distributes and delivers the coordinate increment value of <=1 dot if remaining with the 1-step preceding segment to each DDA. Thus each DDa calculates the coordinates of those dots forming a segment of each allotment based on each data and starts a writing access to a memory chip on the frame memory which takes charge of the coordinates. In this access mode (n) pieces of DDA work at a time and in parallel with a set of four memory chips set within a (4X4) subarray where the start point of the segment of each allotment set the lower left side.
Inventors:
KINUGASA TOSHIMITSU
FUJISAKI TATSUYA
FUJISAKI TATSUYA
Application Number:
JP2516386A
Publication Date:
August 11, 1987
Filing Date:
February 06, 1986
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06T11/20; (IPC1-7): G06F15/62
Attorney, Agent or Firm:
Sadaichi Igita