PURPOSE: To shorten the access time and to decrease the burden necessary to rearrange the data by converting the output of an address arithmetic circuit based on the comparing result of a comparing circuit and the contents of the data fetched into a data latch circuit.

CONSTITUTION: After a DMA cycle signal 102 is active, a first read control signal 101 is active, and then, the comparing action of a comparing register 6 is instructed. At this time, when the contents of 8 low order bits of a counting register 1 and a comparing register 6 are both OOH, a coincidence detecting signal 104 is made active. A modifier table 5 latches the data on a data bus by the coincidence detecting signal 104. At this time, when the data on a data bus 105, namely, the contents of the data to be DMA-transferred by the reading control signal 101 are 1EH, 801EOOH is outputted to a bus 109 by the modifier table 5. The contents of an address register 3 are changed to 801EOOH with the timing specified by the coincidence detecting signal 104.