Title:
メモリセルユニットアレイ
Document Type and Number:
Japanese Patent JP6640097
Kind Code:
B2
Abstract:
In a memory cell unit array, memory cell units each constituted of first wires, second wires, and a nonvolatile memory cell are arranged in a two-dimensional matrix form in a first direction and a second direction. Each of the memory cell units includes a control circuit below it. The control circuit is constituted of a first control circuit and a second control circuit. The second wires are connected to the second control circuit. Some of the first wires that constitute the memory cell unit are connected to the first control circuit that constitutes this memory cell unit. Others of the first wires are connected to the first control circuit that constitutes an adjacent memory cell unit adjacent thereto in the first direction.
Inventors:
Haruhiko Terada
Kitagawa Makoto
Kitagawa Makoto
Application Number:
JP2016550002A
Publication Date:
February 05, 2020
Filing Date:
July 16, 2015
Export Citation:
Assignee:
Sony Semiconductor Solutions Corporation
International Classes:
H01L27/10; G11C13/00; H01L21/8239; H01L27/105; H01L27/11509; H01L45/00; H01L49/00
Domestic Patent References:
| JP2009223971A | ||||
| JP2011154754A |
Attorney, Agent or Firm:
Takahisa Yamamoto
Masaaki Yoshii
Masaaki Yoshii