Title:
メモリ回路デバイス及びその使用方法
Document Type and Number:
Japanese Patent JP7114096
Kind Code:
B2
Abstract:
A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
Inventors:
Takahiro Hanyu
Suzuki Daisuke
Hideo Ohno
Tetsuro Endo
Suzuki Daisuke
Hideo Ohno
Tetsuro Endo
Application Number:
JP2019542315A
Publication Date:
August 08, 2022
Filing Date:
September 14, 2018
Export Citation:
Assignee:
Tohoku University
International Classes:
G11C11/16; G06F5/10; G06F12/02; G11C7/06; G11C8/10; H03K19/17728
Domestic Patent References:
| JP273591A | ||||
| JP201313059A | ||||
| JP201759679A | ||||
| JP61269288A | ||||
| JP200011637A |
Attorney, Agent or Firm:
Patent Attorney Drite International Patent Office
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