Title:
MEMORY CIRCUIT HAVING WIRING ROUTE SUITABLE FOR MOUNTING TEST, ITS TESTING METHOD, AND WIRING EQUIPMENT
Document Type and Number:
Japanese Patent JP3553736
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a memory circuit provided with wiring which facilitates a test, its testing method and its wiring equipment.
SOLUTION: This memory circuit is provided with an MEMC 11 having a first terminal group which is subjected to bus connection, and a storage device 12 having a second terminal group which is subjected to bus connection. A plurality of lines connecting terminals one to one between the first and the second terminal groups are arranged. Two lines connected with adjacent two terminals in the first terminal group are connected with two terminals which are not adjacent to each other in the second terminal group. When short-circuit between terminals occurs in either terminal group, the terminal group to which the short-circuit part belongs can be simply defined by the above constitution.
Inventors:
Yoshiyuki Saito
Takahiro Watanabe
Takahiro Watanabe
Application Number:
JP17966896A
Publication Date:
August 11, 2004
Filing Date:
July 09, 1996
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G01R31/28; G01R31/317; G06F17/50; G11C5/06; G11C29/00; G11C29/02; G11C29/56; H01L21/8242; H01L27/108; H05K13/08; (IPC1-7): G01R31/317; G01R31/28; G06F17/50; G11C29/00; H01L21/8242; H01L27/108
Domestic Patent References:
| JP7105272A | ||||
| JP6249919A | ||||
| JP7320499A | ||||
| JP63255899A | ||||
| JP5289600A | ||||
| JP5203706A | ||||
| JP2236675A | ||||
| JP5157816A |
Attorney, Agent or Firm:
Shiro Nakajima