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Title:
MEMORY CIRCUIT WITH SELF-CHECKING FUNCTION
Document Type and Number:
Japanese Patent JPH0764871
Kind Code:
A
Abstract:

PURPOSE: To obtain a circuit in which a program can be immediately and rapidly executed by a processor, and plural memories can be simultaneously checked by checking the memories with a hardware without any operation of software by the processor.

CONSTITUTION: At the time of power supply or in an arbitrary timing, a switching control signal 101 is outputted from a checking part 1, and a switching part 2 is switched to inside connection. Then, the checking part 1 writes arbitrary inside data 109 for checking in a memory cell 3 by an inside writing signal 107 with an inside address 108 and also writes the data in a register (1) 4. Next, the checking part 1 reads the data of the memory cell 3 by an inside reading signal 106 from the same address as that at the time of writing the data in the memory cell 3, and preserves the data in a register (2) 5 as the reading data 108. The checking part 1 operates one series of operation from the start address of the memory cell 3 of the final address, ends the checking operation at the time of reaching the final address, and switches the switching part 2 to an outside input connecting state.


Inventors:
WATANABE TSUTOMU
Application Number:
JP21326393A
Publication Date:
March 10, 1995
Filing Date:
August 30, 1993
Export Citation:
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Assignee:
NIPPON DENKI MUSEN DENSHI KK
International Classes:
G06F12/16; (IPC1-7): G06F12/16
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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