PURPOSE: To speed up and stabilize a circuit operation by providing plural differential amplifying circuit, first and second input/output bus lines, an output amplifying circuit, and first and second decoding means.

CONSTITUTION: An I/O bus consists of an I/O 13 and the inverse of I/the inverse of O 13', and column decoders (COLUMN.DEC) 15 and 15' to selectively connect digit lines 16 and 16' to the I/O bus 13 and the inverse of I/the inverse of O bus 13' are provided. Further since the input line of an amplifier 14 is the I/O bus and the inverse of I/the inverse of O bus 13', the input signal of the ampli fier 14 surely becomes the differential signal. Consequently an initialized level VM-ΔV of the amplifier 14 is made unnecessary. Thus it is made unnecessary to control the initialized level at the joint of the amplifier 14, futher the activat ing timing of the amplifier 14 is made simultaneous, and the access time can be sped up.