Title:
MEMORY CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH07122065
Kind Code:
A
Abstract:
PURPOSE: To refresh DRAMs at different timings with each of plural banks in order to suppress noise by reducing current consumption and to constitute simple circuitry.
CONSTITUTION: Timing signals of different timings are outputted in accordance with a basic refresh signal from a counter 2 and the refresh control signals for each of the banks are outputted from the output from a control register 3 and the timing signals by a bank separation circuit 4. This memory control circuit outputs the refresh signals by each bank from the refresh control signal and the basic refresh signal in a bank control circuit 5.
Inventors:
SHIMURA HIDEO
MATSUI AKIO
YUYAMA MIKI
MATSUI AKIO
YUYAMA MIKI
Application Number:
JP28412393A
Publication Date:
May 12, 1995
Filing Date:
October 20, 1993
Export Citation:
Assignee:
KOKUSAI ELECTRIC CO LTD
International Classes:
G11C11/406; G06F12/00; (IPC1-7): G11C11/406; G06F12/00
Attorney, Agent or Firm:
Kiyotaka Sakamoto (1 outside)
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