PURPOSE: To suppress only the access of a CPU device which requires interlocking control to a memory bus and to prevent the interruption of access to a memory bus which does not require interlocking control so as to improve the processing efficiency of a system by suppressing access from the other CPU device to the memory bus while a flag is raised.

CONSTITUTION: When the central processing unit 5 of CPU 0 (1) issues an interlocking flag set request, it is inputted to a D-type flip flop circuit 31. Then, an AND signal from both signal lines SETINTL of CPU 0 (1) is outputted from an OR circuit 35 through an AND circuit 32. When CPU 0 (1) is selected, the logical level of a signal line INTL0 becomes a low level and the interlocking request of CPU 1 (2) is suppressed. When the logical level of the signal line INTL1 becomes a high level, the interlocking flag is set in a flip flop circuit 34 and the interlocking request from the other CPU 1 (2) is suppressed.