PURPOSE: To check the imperfection of a writing instruction after a CPU finishes the plural writing instructions and to attain retry in case of the imperfection by providing a timer.

CONSTITUTION: After a writing error FF8 is set to 0, a CPU1 executes transmission through a bus 2 and a memory control device 3 selects an EEPROM 4. Then, the writing instruction is executed. The ROM 4 causes an R/the inverse of B signal to be 0 and executes the writing instruction. When there is no next instruction even after a constant time (t), the signal is returned to be 1. A timer 5 to receive the instruction executes time counting by an internal counter 6 and when there is the next instruction before the time (t) passes, the time counting is executed again. When there is no instruction after the (t) seconds, an FF 7 is caused to be 1 and when the writing of the ROM 4 is finished, the FF 7 is returned to be 0. When a logical circuit 9 recognizes the imperfection of the writing, the writing error FF 8 is set to 1. The CPU successively executes the writing instruction to the ROM 4 and when the instruction is finished, the FF 8 is read through the bus 2. In case that the contents of the FF 8 are 1, it is judged as the writing imperfection and reloading is executed.