Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS5882345
Kind Code:
A
Abstract:

PURPOSE: To perform efficient memory control over pattern data, by selecting a memory circuit according to a changeover flag bit added to the head or tail of data, and outputting pattern data consisting of different-bit-length data in combination.

CONSTITUTION: When a control part 1 performs access to a memory circuit 3a through an address circuit 2a firstly to output one pattern, a switching circuit 5 sends a signal to a selecting circuit 4, and a gate A selects readout data from a memory circuit 3a to obtain an output signal. In this case, the selecting circuit 4 and address circuits 2a and 3b are switched according to flag bits added to memory circuits 3a and 3b to sent contents out of the memory circuits 3a and 3b, so that pattern data is outputted from the selecting circuit 4 automatically.


Inventors:
KANEKO AKIRA
Application Number:
JP18053881A
Publication Date:
May 17, 1983
Filing Date:
November 11, 1981
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
G06F11/22; G06F11/263; G11C29/10; G11C29/56; (IPC1-7): G06F11/22; G11C29/00
Attorney, Agent or Firm:
Koshiro Matsuoka