PURPOSE: To attain the transfer of data at a high speed in a read mode with use of a low-speed memory element by writing data on the low-speed memory elements which are selected successively and then reading out those data collectively with the same address.

CONSTITUTION: A prescribed lower bit of an address given from a microprocessor unit is decoded by a decoder 16, and low-speed memory elements 11W14 are selected successively via OR gates 17W20. Then data are written on elements 11W14 with the same address sent from a driver 15. These data receive the access from the same refresh address given from a CRT controller via an address driver 21. Then the data are read simultaneously and collectively out of the elements 11W14 which are selected en bloc by the CRT controller. Thus it is possible to transfer data at a high speed in a read mode by means of the low- speed memory elements.