PURPOSE: To improve the memory bus application ratio by receiving a memory access request as long as a memory bus is idle.
CONSTITUTION: In the course of a read operation to a memory A, by utilizing a fact that an idle time is generated in a memory bus before the sending of a read data is started after an address is sent out, a write access request to a memory B is received, and an address and write data are sent out. That is to say, a memory request receiving control part 14 decides whether the requested memory is being operated or not, and whether the use time of a memory bus 20 overlaps or not, and when it is decided that the memory concerned is not being operated, and also the use time of the memory bus 20 does not overlap, an accepting signal is sent back to an access origin, a memory starting signal is sent to the control part of the memory concerned side, and a memory start instruction is executed. When the accepting signal is received, the memory access origin sends out an address to the memory bus 20.
TAKAGI TOSHIYUKI
NISHI TOMOYA
| JPS57108952A | 1982-07-07 | |||
| JPS61239341A | 1986-10-24 |
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