Title:
MEMORY CONTROLLER HAVING PROGRAMMABLE TIMING
Document Type and Number:
Japanese Patent JP3521941
Kind Code:
B2
Abstract:
PURPOSE: To provide a memory controller having programmable timing from which a memory signal having programmable timing can be obtained and which can be applied to a system having different clock frequencies and memory timing conditions.
CONSTITUTION: One of the selectors 32, 34, 36, 38, 40, and 42 of a DRAM control unit 24 in a memory controller selects a timing control parameter in accordance with a value from the timing control bit of a control register 30A in the memory controller and one of timing control units 33, 35, 37, 39, 41, and 43 generates the programmable timing control signal at the timing of the memory controller from the timing control parameter and a memory signal containing an address signal and a control signal in corresponding to the selected timing control parameter.
Inventors:
Dresser, Scott A.
Application Number:
JP23900693A
Publication Date:
April 26, 2004
Filing Date:
August 31, 1993
Export Citation:
Assignee:
HEWLETT PACKARD CO <HP>
International Classes:
G06F12/00; G06F12/02; G11C7/22; G11C8/18; G11C11/4076; (IPC1-7): G06F12/00; G06F12/02
Attorney, Agent or Firm:
大西 昭広
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