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Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JPH05189297
Kind Code:
A
Abstract:

PURPOSE: To realize a memory controller to maintain the consistency of memory access in a system provided with plural processors and a shared memory.

CONSTITUTION: A memory managing means 10 to manage the memory access is installed between a shared memory means 3 and a first and a second memory requesting means 1, 2. When the request of the read-out or the write-in of data is generated from the memory requesting means 1, 2 to the memory means 3, an access area registering means 10 decodes memory request size, and registers beforehand the access area of the memory means 3. Besides, when the memory requests are generated at a time to the memory means 3 from plural memory requesting means, an access area coincidence discriminating means 12 discriminates whether these access areas coincide with each other or not, and instructs the priority order of access processing. Next, a memory request size updating means 13 updates the request size at every access.


Inventors:
MASUNO TAKASHI
Application Number:
JP2623292A
Publication Date:
July 30, 1993
Filing Date:
January 16, 1992
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F12/02; G06F12/00; G06F12/04; (IPC1-7): G06F12/02
Attorney, Agent or Firm:
Yoshiki Okamoto



 
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