PURPOSE: To reduce a circuit scale by controlling dynamic memories at different speeds without providing any dedicated circuit inside a circuit.

CONSTITUTION: When the start of a cycle at a CPU 5 is detected, a CPU decoder cycle tracer 1 judges the classes of dynamic memories 6a and 6b based on an external signal. A memory sequencer 2 outputs a signal corresponding to class information from the CPU decoder cycle tracer 1 to the dynamic memories 6a and 6b, generates the address of a timing parameter corresponding to the class information, outputs it to a ROM 3 and instructs the load of the timing parameter to a counter 4 at required timing. When counting up to the value of the timing parameter from the ROM 3 is completed, the counter 4 reports the end of the count operation to the memory sequencer 2. It is reported from the memory sequencer 2 to the CPU decoder cycle tracer 1 that a series of memory control is completed.