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Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JPS60171526
Kind Code:
A
Abstract:

PURPOSE: To attain the self-diagnosis for the working of an ECC (error detection/correction) circuit with no use of a fixed disk device, by providing a buffer circuit to store data by a data switching circuit in a diagnosis mode and destructing the data partly by a control circuit.

CONSTITUTION: When the working of an ECC circuit 5 is diagnosed, the data flowing route is first changed by a data switching circuit 7 so that the data stored in a data buffer circuit 2 is delivered to a buffer circuit 6. Then the data stored in the circuit 6 is destructed partly by a control circuit 1, and the data destructed partly is supplied to the circuit 2 from the circuit 6 and then compared with the first data. If coincidence is obtained from said comparison, it is decided that the circuit 5 is adding a check bit to the output data and checking and correcting an error of the input data in a normal way.


Inventors:
MISHIMA YASUNARI
Application Number:
JP2717884A
Publication Date:
September 05, 1985
Filing Date:
February 17, 1984
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F12/16; G06F3/06; G06F11/10; G11B20/10; G11B20/18; (IPC1-7): G06F3/06; G06F11/10; G06F12/16; G11B20/10
Attorney, Agent or Firm:
Soga Doteru



 
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