Title:
MEMORY DEVICE AND FORMATION METHOD FOR THE SAME
Document Type and Number:
Japanese Patent JP2022027599
Kind Code:
A
Abstract:
To provide a memory device and a formation method for the same.SOLUTION: An SRAM array, which is a semiconductor device, includes a plurality of first memory cells in a memory region, and a first blocking transistor T7 in a dummy region 150 adjacent to the memory region. Each first memory cell includes a static random access memory (SRAM) 20. The SRAM cell includes a first pull-down transistor T1 and a second pull-down transistor T2. First source/drain regions of the first pull-down transistor and the second pull-down transistor in the first memory cells are electrically connected to a first source/drain region of the first blocking transistor. The first blocking transistor has a second source/drain region electrically connected to the power source voltage. The power source voltage is grounded.SELECTED DRAWING: Figure 2C
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Inventors:
YANG ZHI QUAN
Application Number:
JP2021123321A
Publication Date:
February 10, 2022
Filing Date:
July 28, 2021
Export Citation:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTUARING CO LTD
International Classes:
H01L21/8244
Attorney, Agent or Firm:
Choi Hailong
Takayuki Kawai
Takayuki Kawai