Title:
MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH10125064
Kind Code:
A
Abstract:
To speed up operation of a sense amplifier through amplification of signal read from a memory cell by boosting up a threshold voltage using a voltage setting circuit to control a substrate voltage of a transistor forming the sense amplifier.
A sense amplifier S/A is activated by the signals SAP and /SAN under the condition that the potential of substrate terminals of four transistors Qn1, Qn1, Qp1, Qp2 is 0.5 × VCC. In this case, the sense amplifier S/A senses and amplifies only a light change of voltage of the bit line explained above and also amplifies the potentials of the bit line pair BL and/BL respectively to H and L levels. As explained above, data is read from the memory cell.
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Inventors:
IMAI YOSHIRO
TSUCHIDA KENJI
TSUCHIDA KENJI
Application Number:
JP27069596A
Publication Date:
May 15, 1998
Filing Date:
October 14, 1996
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G11C11/409; G11C11/408; (IPC1-7): G11C11/409
Attorney, Agent or Firm:
Togawa Hideaki