PURPOSE: To detect correctness of the parity bit data by using a write inverting means to switch selectively the parity bit data produced by a parity bit generat ing means and then a read inverting means to invert selectively the polarities of the parity bit data read out of a memory cell.

CONSTITUTION: A parity generator 16 supplies the produced parity data to the input terminal of a write polarity inverting gate 3. A parity polarity switching circuit 1 inverts selectively the parity data based on the value set at the host side or writes the parity data into a memory cell 18 with no inversion. In a read mode of the parity bit, the parity are corresponding to a selected memory cell train is supplied to the input terminal of a polarity inverting gate 6. A parity polarity switching circuit 4 inverts selectively the parity data based on the value set at the host side or write the parity data into a parity error detector 24 with no inversion. Thus a parity detecting function is inspected.