PURPOSE: To prevent the contents of memory read-out from being corrected mistakenly by correcting the output of the memory read-out only when an error correcting code in a memory error correcting circuit and a memory parity error occur simultaneously.

CONSTITUTION: An error correcting code is added to memory writing data (a) in an encoder/decoder (E/D) 2 through a register 1 to be outputted as a data (d), and to be outputted as a parity code (h) from a parity generating circuit 3. The data (d) is written in a memory 7, returned to the register 1 as an output (g) through a buffer 6 as an output (f), and divided into a data bit (b), error correcting code (c), and parity bit (i). The data bit (b) is sent to the E/D 2, the circuit 3, and a correcting circuit 8. The E/D 2 generates a correcting signal (k), the bit (i) and the parity code (h) generated in the circuit 3 are outputted as a parity error signal (j), and the signal (k) and the data bit (b) are inputted to the correctin circuit 8 to output a memory read-out data (l).