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Title:
MEMORY FORMATION SYSTEM FOR DATA FORMAT CONVERSION
Document Type and Number:
Japanese Patent JPS60218925
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of using ICs and also to attain reduction of power consumption and the high-speed data processing, by providing a data line passing through a submemory for a buffer memory formation method applied when the serial data are rearranged to the parallel data.

CONSTITUTION: An RAM10 and a submemory 15 are excluded out of a conventional submemory 14, and instead a data line DL passing through a submemory 22 is provided newly. The serial data 7 are fetched successively to RAM23∼25, and the data to be fetched to the RAM10 is supplied directly to an RAM27 of a main memory 26. At the same time, the data on RAM23∼25 are transferred to the RAM27 for formation of the data on the RAM27. In other words, the data to be supplied to the RAM10 is supplied to the RAM27 through the memory 22 and also to both RAM28 and 29 for formation of parallel data on (n)a channels. Here the n-th data is sent through if n/m is not equal to a natural number.


Inventors:
IDA YUKIO
Application Number:
JP7495884A
Publication Date:
November 01, 1985
Filing Date:
April 16, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03M9/00; H04L13/00; H04L29/06; (IPC1-7): H03M9/00; H04L13/00
Attorney, Agent or Firm:
Akio Takahashi



 
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