To obtain a memory in which both a write operation and a read operation are executed in parallel so as to enhance an execution speed by a method wherein, when a read request comes during the write operation, an interrupt processing operation which reads out data which is written into a memory cell at an address whose read operation is requested is executed.

During the execution of a write operation, a read request is input to a control circuit 5 from the outside. Then, when a data bus 4 is performing operations other than a latch operation, the bus 4 becomes an empty state, and the output of an address latch circuit 9 is stopped. At the same time, address data which is contained in the read request is latched, and data which is written into addresses at a memory cell array 10 on the basis of the address data is read out. That is to say, the execution of the write operation is interrupted once during a read operation, and the execution of the write operation is resumed after the finish of the read operation. In this manner, when the read request comes during the execution of the write operation, the circuit 5 performs an interrupt processing operation which reads out the data written into the address during the read request of the array 10. As a result, both the write operation and the read operation can be executed in parallel, and the execution speed of a memory can be enhanced.