Title:
メモリインターフェースシステム
Document Type and Number:
Japanese Patent JP4603282
Kind Code:
B2
Abstract:
The invention relates to a semiconductor memory device and, more particularly, to an interface system for a semiconductor memory device. The interface includes a transmitter capable of encoding first and second input signals as a plural-bit symbol signal responsive to first and second clocks, respectively, the first clock being out of phase from the second clock. And the interface includes a receiver capable of generating first and second output signals by decoding the symbol signal responsive to third and fourth clocks, respectively. Other embodiments are illustrated and described.
Inventors:
Cui Jean Fan
Application Number:
JP2004107329A
Publication Date:
December 22, 2010
Filing Date:
March 31, 2004
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
H04L12/20; G06F13/00; H04L25/49; G06F13/16; G06F13/42; G11C7/10; G11C7/22; H03M5/02; H04L5/04; H04L25/02
Domestic Patent References:
| JP2002281095A | ||||
| JP8031101A | ||||
| JP5037494A | ||||
| JP2007525061A |
Attorney, Agent or Firm:
Makoto Hagiwara