PURPOSE: To shorten initialization time by inhibiting or invalidizing the operation of a defective address memory corresponding to a signal from an inhibition circuit provided at a redundant circuit when there is no defect in a main memory.

CONSTITUTION: An address decoder DEC receives an address ADD and access to the specified block of a main memory MP is performed. When no defect is detected in the entire main memory MP by a test, a signal INH is sent from an inhibition circuit IN to a defective address memory CAM and its operation is made inactive. When an enable signal VAL is outputted to the circuit IN without transmitting this signal INH, the address ADD transmitted to the memory CAM as well is compared with all the stored defective addresses. When any address is coincident, the address memory block of the main memory MP is prevented from being addressed by a signal ADR outputted from the memory CAM and in place of that block, the block of the redundant memory MR is addressed.