Title:
MEMORY SELF-TESTING METHOD
Document Type and Number:
Japanese Patent JP3463127
Kind Code:
B2
Abstract:
PURPOSE: To enable the self-testing of an EEPROM or the like by respectively imparting a checking function to a read/write area and a read-only area and utilizing the setting data of the other area when one of them is judged as defective.
CONSTITUTION: The controller 2 of a system generally manages and controls the respective parts of a picture information controller 5, a storage device 4, a printer 6 and the EEPROM 3 storing the setting data for sequence storage control, a picture conversion processing and temperature control, etc., by a key input or the like. The EEPROM 3 is provided with the plural pairs of the read 7 write area for which a user is capable of freely changing data contents and the area exclusively for reading the data and the respective areas are provided with the checking function. Then, when even one of the pair of the areas is judged as defective, the setting data of the other area of the pair are copied and when it is still defective, the setting data of the other area of the pair are utilized as well. Thus, the sufficient testing of the EEPROM 3 and a sufficient margin for an unexpected situation are obtained.
Inventors:
Mitsuyasu Nakajima
Application Number:
JP9445194A
Publication Date:
November 05, 2003
Filing Date:
May 06, 1994
Export Citation:
Assignee:
CASIO COMPUTER CO.,LTD.
International Classes:
G06F12/16; (IPC1-7): G06F12/16
Domestic Patent References:
| JP2245953A | ||||
| JP59231798A |
Attorney, Agent or Firm:
Takehiko Suzue