To provide a memory sharing system that enables memory sharing between a CPU and custom hardware even if using a general purpose chipset and memory.
The memory sharing system 10, which has the CPU 12, the custom hardware 16, the ROM 22 for the CPU 12, and the general purpose CPU chipset 14 for connecting them, and shares the ROM 22 between the CPU 12 and the custom hardware 16, comprises a ROM arbiter 20 that, as an arbitration means connected between the CPU chipset 14 and the ROM 22 to arbitrate access from the CPU 12 and custom hardware 16 to the ROM 22, sends to the CPU 12 a relative zero jump instruction for reaccess to a given address of the ROM 22 when the CPU 12 requests access to the given address while the custom hardware 16 is permitted to access the ROM 22.
Kato Kazunori
Katsuichi Nishimoto
Hiroshi Fukuda