Title:
MEMORY, MEMORY SUB-SYSTEM, MEMORY DEVICE AND MEMORY SYSTEM ADDRESSING METHOD
Document Type and Number:
Japanese Patent JP2968486
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To efficiently transfer the data by comparing a received selection bit with a stored selection bit and making possible accessing an addressed cell among memory cells in response to that.
SOLUTION: Each bank 201 is provided with a contents addressing enable memory cell array 207, and the array 207 is provided with many CAM cells. When a bank selection bit BNKSL on a bank selection bus 210 coincides with an address bit stored in a prescribed array 207, an answering address buffer/ latch 206 is enabled by the coincidence line 211 of the array 207. Then, a column address bit supplied to an address bus 209 is inputted to a latch 206 to be latched. Then, data access to an answering cell array 202 is performed through answering a row decoder 203 and a column decoder 205.
Inventors:
JII AARU MOHAMU RAO
Application Number:
JP30686996A
Publication Date:
October 25, 1999
Filing Date:
November 18, 1996
Export Citation:
Assignee:
SHIIRASU ROJITSUKU INC
International Classes:
G11C11/401; G11C15/04; G11C11/41; (IPC1-7): G11C15/04; G11C11/401; G11C11/41
Domestic Patent References:
| JP1311339A | ||||
| JP1331340A | ||||
| JP3232186A | ||||
| JP7105082A | ||||
| JP6313497U |
Attorney, Agent or Firm:
Shusaku Yamamoto