Title:
メモリシステム
Document Type and Number:
Japanese Patent JP4082913
Kind Code:
B2
Abstract:
The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
Inventors:
Shigemasa Shioda
Hiroyuki Goto
Shibuya Hiroshi
Ikuo Hara
Yasuhiro Nakamura
Hiroyuki Goto
Shibuya Hiroshi
Ikuo Hara
Yasuhiro Nakamura
Application Number:
JP2002030191A
Publication Date:
April 30, 2008
Filing Date:
February 07, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F12/00; G06F3/08; G06F13/16; G06F13/38; G11C7/10
Domestic Patent References:
| JP4287261A | ||||
| JP2001357684A | ||||
| JP200224081A | ||||
| JP6103026A | ||||
| JP5265939A | ||||
| JP11191297A |
Foreign References:
| WO2001044957A1 |
Attorney, Agent or Firm:
Shizuyo Tamamura