Title:
Memory systems using regression analysis and how to read them
Document Type and Number:
Japanese Patent JP6345407
Kind Code:
B2
Abstract:
A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.
Inventors:
Kim Hiroki
Gong Shun Town
Xu Kei
Hiroshi Son
Gong Shun Town
Xu Kei
Hiroshi Son
Application Number:
JP2013220910A
Publication Date:
June 20, 2018
Filing Date:
October 24, 2013
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C16/08; G11C11/56; G11C16/04
Domestic Patent References:
| JP2012133832A | ||||
| JP2003298877A | ||||
| JP2002526717A |
Foreign References:
| US20110044101 | ||||
| US20100296350 |
Attorney, Agent or Firm:
Shinya Mitsuhiro