To provide a memory testing device capable of performing, at high speed, logical comparison of output patterns which are time-divided in a cycle.

When receiving signal output from a PDS (Programmable Data Selector) 20, an expected value select circuit 45 selectively outputs any two separated expected value patterns, EXP 1 and EXP 2. A logical comparison circuit 55 receives the expected value patterns, EXP 1 and EXP 2, and logical output of a tested memory 70 to logically compare them in separated two systems. Thereby, logical comparison using two expected values in one cycle can be performed.