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Title:
METAL BASE TRANSISTOR
Document Type and Number:
Japanese Patent JPS639149
Kind Code:
A
Abstract:

PURPOSE: To manufacture a metal base transistor with high performance and excellent reproducibility while enabling the height and shape of collector barrier to be freely controlled by a method wherein a metal and a thin semiconductor layer are brought into ohmic contact with each other to form a collector barrier by hetero junction or planar doping of the thin semiconductor layer and the second semiconductor.

CONSTITUTION: A normalconducting or superconducting metallic base layer 34 whereon a carrier injected from an emitter 35 is running, the first semiconductor layer 33 in ohmic contact with the metallic base layer 34 in thickness exceeding 1 atomic layer and not exceeding 20 atomic layers and the second semiconductor layer 31 comprising a collector are provided. Furthermore, a barrier layer 32 formed by the heterojunction of the first semiconductor layer 33 and the second semiconductor layer 31 or formed by planar doping process is formed between the first semiconductor layer 33 and the second semiconductor. layer 31. For example, an N+- In0.52 Gd0.48As epitaxial layer 31 1 μm thick, a non- doped In0.52Ag0.10Ga0.38As layer 32 100μm thick, an N+In0.52 Ga0.48As layer 33 5 μm thick, a base 34 comprising an Al thin film and an emitter 35 etc. comprising Al thin film are formed on a semiinsulating InP substrate 30.


Inventors:
TAMURA YASUTAKA
Application Number:
JP15348586A
Publication Date:
January 14, 1988
Filing Date:
June 30, 1986
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/80; H01L29/205; H01L29/36; H01L29/68; H01L29/76; H01L39/22; (IPC1-7): H01L29/205; H01L29/68; H01L29/80; H01L39/22
Attorney, Agent or Firm:
Kugoro Tamamushi



 
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