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Title:
METHOD AND CIRCUIT FOR POLISHING
Document Type and Number:
Japanese Patent JPH05219093
Kind Code:
A
Abstract:

PURPOSE: To provide the polishing circuit for controlling the traffic which flows in violation of a report, and especially, the method for executing the detection of high accuracy by a simple constitution, in a network using an asynchronous transfer mode.

CONSTITUTION: A VP/VC distributing circuit 2 distributes an ATM cell from an entry interface 1 to a traffic monitor circuit block 3 in accordance with a virtual path identifier or a virtual channel identifier. Plural counters 4-1 and 4-2 of the circuit block 3 are reset in a period T, and also, with a time shift of T/2, respectively. Comparators 5-1, 5-2 compare a counting value of each corresponding counter 4-1, 4-2 with a threshold X, and give an instruction to a rejection control circuit 9, when the counting value of either counter exceeds the value of X. Accordingly, the burst detection capacity of the polishing circuit can be doubled by a simple constitution, and the network can be utilized effectively.


Inventors:
TAKASE MASAHIKO
SHINADA SHIGEO
TAKANO MITSUHIRO
OUCHI TOSHIYA
YAMANAKA NAOAKI
SATO YOICHI
Application Number:
JP2097492A
Publication Date:
August 27, 1993
Filing Date:
February 06, 1992
Export Citation:
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Assignee:
HITACHI LTD
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04L47/20; H04Q11/04; (IPC1-7): H04L12/48
Attorney, Agent or Firm:
Ogawa Katsuo



 
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