Title:
METHOD FOR CLOCK SUBORDINATE SYNCHRONIZATION
Document Type and Number:
Japanese Patent JP2518148
Kind Code:
B2
Abstract:
PURPOSE: To provide a clock subordinate synchronization method providing a stable output clock signal regardless of phase fluctuation of an input clock signal.
CONSTITUTION: A phase comparator 1 compares an input clock signal with a frequency division signal of an output clock signal and the result is converted into a phase difference quantity and the direction of the phase difference is decided by a digital filter 2. A frequency phase control circuit 3 implements frequency lock control and phase lock control based on a predetermined control variable in response to the direction of the phase difference. A voltage controlled oscillator 5 is controlled by a control signal obtained by adding results of both controls to provide the output clock signal.
Inventors:
NEZU TOSHA
Application Number:
JP7747593A
Publication Date:
July 24, 1996
Filing Date:
March 12, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H03L7/113; H03L1/02; H03L7/093; H03L7/14; H04L7/00; (IPC1-7): H03L7/113
Domestic Patent References:
| JP410711A | ||||
| JP6336613A | ||||
| JP5237756A | ||||
| JP5320980Y2 |
Attorney, Agent or Firm:
Masaki Yamakawa