Title:
METHOD FOR CONVERTING INFORMATION BIT WITH ERROR CORRECTING CODE, ENCODER AND DECODER FOR EXECUTING THIS METHOD
Document Type and Number:
Japanese Patent JP3923618
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To utilize a programmable BTC circuit by allowing a receiver to arrange a sample whose absolute value shows highest reliability at the position of an input matrix corresponding to the decided position of a second binary matrix.
SOLUTION: At the time of receiving the sample of a signal R(t), a processor 66 forms an input matrix {R} corresponding to the designated position of Y to prepare matrixes {R'} and {D} to store in a suited address. In basic decoding, suited samples concerning vectors [R'], [D] and [R] are supplied for a basic decoder 65. New values concerning [R'] and [D] are next recorded. In these processing, the processor 66 sequences reading or writing to the memory 67. At the last of m-cycles, the processor 66 sequences reading operation at the suited address of the memory 67 in order to send the output signal Z(t) of the basic decoder 65.
Inventors:
Ramesh Pindia
Patrick Add
Patrick Add
Application Number:
JP26913397A
Publication Date:
June 06, 2007
Filing Date:
August 26, 1997
Export Citation:
Assignee:
FRANCE TELECOM
International Classes:
G06F11/10; H03M13/23; H03M13/00; H03M13/29; H03M13/45; (IPC1-7): H03M13/00; G06F11/10; H03M13/12
Domestic Patent References:
| JP10135849A | ||||
| JP7202722A | ||||
| JP2246440A | ||||
| JP3172026A | ||||
| JP6314474A |
Foreign References:
| EP0827284B1 | ||||
| EP0827285B1 |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Shigeo Naruse
Takashi Watanabe
Shigeo Naruse